Embodiments of the present invention relate to power management for a system including devices coupled via an interconnect.
High performance serial-based interconnect or link technologies such as Peripheral Component Interconnect (PCI) Express™ (PCIe™) links based on the PCI Express™ Specification Base Specification version 1.1 (published Mar. 28, 2005) (hereafter the PCIe™ Specification) are being adopted in greater numbers of systems. PCIe™ links are point-to-point serial interconnects with N differential pairs intended for data transmission with either sideband clock forwarding or an embedded clock provided in each direction. Clock synchronization and data recovery requirements significantly influence the exit latencies of low power state exit and thus impact the effective use of low power states if the serial link always has to be armed for asynchronous bus master traffic. For example, a phase-locked loop (PLL) and a platform reference clock remain energized in the ready state even in the absence of traffic activities. This has a direct and negative consequence on the average power consumption of both devices coupled to the link.
In the PCIe™ Specification, various power saving states are provided for a link (i.e., an interface) of a serial interconnect. Specifically, the specification describes the presence of link states L0, L0s, L1, L2 and L3. The L0 state corresponds to link on and the L2 and L3 states correspond to link off (with the difference being that auxiliary power is present in the L2 state), while the L0s state provides for a low-resume standby latency state, and the L1 state corresponds to a low power standby state. These low power states may be achieved via the Active Status Power Management (ASPM) capability of a PCIe™ interface, which enables an endpoint device to request entry into a low power state. Typically, however, an upstream device such as a core (and its related clocks) remains energized, dissipating significant power.
In many different system types such as server and workstation platforms, idle power dissipation can be a large concern. This is especially so in such platforms including multiple processors, such as a multiprocessor (MP) system, or even a single processor platform including multiple cores. Given the vast computing resources of such processors, oftentimes one or more cores (or even entire processor sockets) may not be performing useful work. However, it remains difficult to place such components into a low power state as it is unknown when new information will need to be processed by the components. While software-managed system power states are increasingly supported, these states can have significant exit latencies which discourage their usage for brief periods of low demand (such as may be measured in fractions to handfuls of seconds, rather than in minutes or hours). Hardware-autonomous mechanisms for power reduction, such as ASPM may be present, however these mechanisms require support on both ends of an interface, and this support can be inconsistent.
Further, serial interfaces implementing autonomous standby and sleep states also commonly include autonomous wake-up without prior software notification. The need to support such traffic without breaking an interface's protocol has historically precluded low power states such as deep-sleep entry by various platform components, including a processor core, irrespective of the duration of inactivity enabling the interface standby states.